Low density parity-check (LDPC) codes were first proposed by Gallager in 1962, and then “rediscovered” by MacKay in 1996. LDPC codes have been shown to achieve an outstanding performance that is very close to the Shannon transmission limit. However it is very difficult to build an efficient hardware implementation of a circuit for decoding LDPC codes. All existing hardware implementations of LDPC decoding algorithms suffer from low speed and large area and power requirements. It is very important to develop an LDPC-decoder that has better speed, area, and power characteristics than the existing implementations.
The most promising algorithm for decoding LDPC-codes is so the called min-sum algorithm. Generally speaking this algorithm performs two main operations                1. Find a minimum number among a given set of signed numbers, and        2. For a given group of signed numbers A1, . . . , AN and a signed number M calculate:Si=S−Ai,wherei=1, . . . N, S=A1+ . . . +AN+M, andSIGN=sign(S)={0, if S≧0; 1, if S<0}.        
A typical hardware implementation of this algorithm represents the LDPC decoder as a set of multiple node processing units performing operations (1) and (2) as given above. There are two types of units:
1. So-called “check node processing units” (CNU) that perform operation (1), and
2. So-called “variable node processing units” (VNU) that perform operation (2).
The decoder may contain up to thousands of these two units working in parallel. One hardware realization of a VNU as depicted in FIG. 1 contains N-input adder module (denoted by the “+” sign) for calculating the total sum S, and N two-input subtractor modules (denoted by the “−” sign) for calculating “partial” sums Si.
What is needed, therefore, is a VNU that improves—at least in part—the speed, area, and power characteristics of the VNU, and therefore enables the construction of a better LDPC decoder.